Method for masking false bound faults in a central processing unit
US5138617A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1990 |
| Grant date | Aug 11, 1992 |
| Priority date | — |
| Expiry date | Feb 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system having a hardware and/or firmware design problem which causes a false boundary error under certain conditions, the subject method serves to handle and correct the false boundary error condition in the operating system. This recovery process is carried out such that the information from which the faulting address was developed is redistributed among a plurality of information components in such a manner that the false boundary error will not recur on retry. Thus, the process masks the problem by remapping the virtual address components of the faulting instruction so that the final virtual address, though identical to the failing one, is processed without fault by the central processor unit during recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.