Symmetric edge true/complement buffer/inverter and method therefor
US5140174A · kind A · utility
11Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1991 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | Jan 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a buffer/inverter which generates symmetric and complementary output signals from a single input signal. The device employs four inverters having similar switching speeds. The true output signal is generated by passing the input signal through two inverters. The complement output signal is generated by passing the true output signal through a third inverter, passing the input signal through a fourth inverter and coupling the outputs of the third and fourth inverters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.