High speed CMOS flip-flop employing clocked tristate inverters
US5140180A · kind A · utility
4Cited by
10References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1990 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | Aug 24, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.