BiCMOS logic circuit with self-boosting immunity and a method therefor
US5140192A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1990 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | Aug 1, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BiCMOS logic circuit with self-boosting immunity comprises a resistor, first and second transistors, a switching portion, and a discharge portion. The resistor and first transistor bias the switching portion to first and second reference voltages, which may be equal. The second transistor is a bipolar transistor providing an output signal to a load. The switching portion couples the bias voltage provided by the resistor and the first transistor to the base of the second transistor in response to a true result of a logic operation on at least one input signal and couples the base of the second transistor to a second power supply voltage terminal in response to a false result of the logic operation. The discharge portion couples the output signal to a logic low or pulldown voltage in response to a false result of the logic operation. In one form, the logic operation is a logical inversion of an input signal. In this case, the switching portion may be provided by a P-channel MOS transistor having first and second current electrodes connected serially between the bias signal and the base of the second transistor, with a gate receiving the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.