Flash writing circuit for writing test data in dynamic random access memory (DRAM) devices
US5140553A · kind A · utility
15Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1990 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | Jan 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash writing circuit for testing of dynamic random access memory (DRAM) devices comprises a generally conventional DRAM device and includes additional elements for writing identical data in each memory cell via bit lines connected to the memory cells but without the use of the conventional I/O lines normally used to write data into the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.