Packet switching system having bus matrix switch
US5140582A · kind A · utility
29Cited by
5References
46Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1991 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | Apr 30, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3018
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet switching system having a matrix switch including input packet transfer buses and output packet transfer buses. Transfer buffers or gates are provided at cross points of the input and output packet transfer buses. An input packet is supplied to the matrix switch through a transfer control circuit, and an output packet from the matrix switch is output through the transfer control circuit. The input packet is permitted to be applied to the matrix switch so that each of the output packet transfer buses has only one packet during one packet transfer cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.