Multi-processing system and cache apparatus for use in the same
US5140681A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | May 23, 1989 |
| Grant date | Aug 18, 1992 |
| Priority date | — |
| Expiry date | May 23, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A main memory is subdivided into a shared region to undergo a write access from a plurality of processors and an input/output device and a plurality of private regions to undergo a write access only from the associated processor. Each of the cache devices includes a region discriminating circuit for determining whether an address generated from the processor is to be employed for an access to the shared region or to the private regions. If the access is to be conducted to the shared region, the cache devices operate according to the write-through method. On the other hand, if the access is to be conducted to the private region, the cache devices operate according to the copy-back method. When the processor or the input/output device rewrites data in the shared region of the main memory, the stored data of the shared region in the cache device of the processor is invalidated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.