Method and apparatus for arranging access of VRAM to provide accelerated writing of vertical lines to an output display
US5142276A · kind A · utility
43Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1990 |
| Grant date | Aug 25, 1992 |
| Priority date | — |
| Expiry date | Dec 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An arrangement for writing to and reading from the random access ports of a multibank frame buffer so that individual pixels to be presented in a vertical line on an output display are arranged sequentially from top to bottom in different banks of the frame buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.