Semiconductor memory device
US5142492A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1990 |
| Grant date | Aug 25, 1992 |
| Priority date | — |
| Expiry date | Oct 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is disclosed which comprises a regular row/column memory cell array having blocks obtained by dividing the memory cell array in the column and row directions, a first peripheral circuit irregularly provided between the blocks divided in the column direction, a second peripheral circuit provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit provided between the first peripheral circuit and the respective block and including a second decoder, and a fourth peripheral circuit provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.