Intercomputer communication control apparatus and method
US5142683A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1991 |
| Grant date | Aug 25, 1992 |
| Priority date | — |
| Expiry date | Oct 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/00
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Interprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate interru…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.