Multiprocessor system having processors and switches with each pair of processors connected through a single switch using Latin square matrix
US5142686A · kind A · utility
6Cited by
14References
1Claims
0Family size
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Key dates
| Filing date | Oct 20, 1989 |
| Grant date | Aug 25, 1992 |
| Priority date | — |
| Expiry date | Oct 20, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17375
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computing system having a plurality of processors 11-23 and a plurality of switches 31-43 is interconnected such that a single one of said switches 31-43 is between any pair of said processors 11-23.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.