Ohmic contact for III-V semiconductor devices
US5144410A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 1991 |
| Grant date | Sep 1, 1992 |
| Priority date | — |
| Expiry date | May 14, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dependable ohmic contact with consistently low specific contact resistance (<1.times.10.sup.-6 .OMEGA.-cm.sup.2) to n-type GaAs (10) is produced by a three or four step procedure. The procedure, which is employed following implantation to form doped regions in the GaAs substrate for contacting thereto, comprises: PA0 (a) adsorbing or reacting sulfur or a sulfur-containing compound (26) with the GaAs surface (10') at locations where the contact metal (28) is to be deposited; PA0 (b) forming a metal contact layer (28) on the treated portions of the GaAs surface; PA0 (c) optionally forming a protective layer (30) over the metal contact; and PA0 (d) heating the assembly (metal and substrate) to form the final ohmic contact. The surface treatment provides a lower specific contact resistance of the ohmic contact. Elimination of gold in the ohmic contact further improves the contact, since intermetallic compounds formed between gold and aluminum interconnects ("purple plague") are avoided. In addition, the absence of gold in the metal improves the reliability of ohmic contacts, and the resulting metal can be patterned by etching or lift-off process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.