Normalization estimator
US5144570A · kind A · utility
12Cited by
13References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1991 |
| Grant date | Sep 1, 1992 |
| Priority date | — |
| Expiry date | Jun 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A normalization circuit (24) which comprises a signed digit subtracter (25) coupled to operand registers (14, 19). The signed digit subtracter (25) subtracts the operands and inputs a signed digit difference to a pseudovalue converter (27). The pseudovalue converter (27) generates a pseudovalue in non-redundant format which contains its most significant non-zero bit in the selected bit position. The pseudovalue is output to a leading zero counter (28) which counts the number of leading zeroes in the pseudovalue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.