Semiconductor memory with substrate voltage generating circuit for removing unwanted substrate current during precharge cycle memory mode of operation
US5146110A · kind A · utility
9Cited by
6References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 1991 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Jul 26, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A semiconductor memory device having a substrate voltage production circuit comprises a time delay circuit. The time delay circuit of the present invention has a simple construction and is provided to facilitate removal of an unwanted substrate current I.sub.SUB existing during a precharge cycle of memory operation. The substrate voltage production circuit requires no additional regulating signals for operation. Latch-up conditions commonly caused by such unwanted substrate currents are eliminated and stable semiconductor memory device operation is achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.