High speed semiconductor memory having a direct-bypass signal path
US5146427A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 21, 1992 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Jan 21, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.