Memory error correction system distributed on a high performance multiprocessor bus and method therefor
US5146461A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1989 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Dec 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1044
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed error correction circuit for a synchronous high performance multiprocessor bus wherein the memory directly transfers data containing error fields to the multiprocessor bus without performing an error check. Each device, such as a plurality of processors or input/output busses, connected to the multiprocessor bus has error correction circuitry located between the multiprocessor bus and the device to perform error correction while the data is being transferred off the multiprocessor bus and stored in data buffers at the bandwidth of the multiprocessor bus. The error correction circuit detects and corrects data errors caused by the memory or the multiprocessor bus. The stored data is later transferred out of the buffers at the bandwidth of the device. Data from a device is delivered into the device buffers at the bandwidth of the device for later delivery of the data into memory at the bandwidth of the multiprocessor bus. During such transfers, the error correction circuitry generates the error field as the device data is transferred onto the multiprocessor bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.