Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register
US5146573A · kind A · utility
27Cited by
11References
8Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 25, 1989 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Oct 25, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.