Refresh control for dynamic memory in multiple processor system
US5146589A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1990 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Dec 17, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed. The refresh cycles are interposed at the same point in the instruction stream for each of the three CPUs by counting instruction execution cycles separately in each CPU, and interrupting to do a refresh cycle when a given count is reached. Stall cycles are also counted, and w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.