Structure and process for fabricating conductive patterns having sub-half micron dimensions
US5147740A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1990 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Aug 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mask and lithographic process is disclosed for the formation of conductive patterns on substrates, particularly in connection with the formation of high electron mobility transistors (HEMT) and metal-semiconductor field effect transistors (MESFET). The technique allows the formation of sub-half micron conductive patterns on semiconductor substrates using optical lithography and a multilayer portable conformable mask. The method includes the application of optical contact lithography to a conventional photoresist followed by a deep UV flood exposure of an underlying multilayer PMGI portion. Metal is deposited on a semiconductor substrate through the mask formed by the photoresist and PMGI layers to produce sub-half micron conductive patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.