Fabrication method for a sub-micron geometry semiconductor device
US5147812A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1992 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Apr 1, 2012 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/943
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a sub-micron geometry semiconductor device using a chromeless mask. An optical exposure system (22) directs light through a chromeless mask (21). The chromeless mask (21) uses destructive interference of light to pattern a light sensitive material (32) on a semiconductor wafer (28). Phase differences in light passing thru chromeless mask (21) creates dark regions which form a non-exposed area of light sensitive material (37). The exposed light sensitive material is removed. The non-exposed area of light sensitive material (37) which remains, protects the gate material underneath it, as all other gate material is removed from the wafer. The non-exposed area of light sensitive material (37) is removed leaving a sub-micron gate (39). A drain and source is then formed to complete the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.