Third order sigma delta oversampled analog-to-digital converter network with low component sensitivity
US5148166A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 10, 1990 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Jul 10, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/414
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved modulator network for an interpolative oversampled (sigma-delta) analog-to-digital converter comprises a second-order modulator, which performs double integration of error between its digital output signal and its analog input signal, and a first-order modulator, which performs single integration of error between its digital output signal and an analog signal supplied thereto from the second-order modulator. The modulators supply their output signals to a digital error cancellation circuit which suppresses in the signal supplied to a decimation filter the quantization noise arising in the second-order modulator. The network exhibits significantly reduced sensitivity to the practical nonidealities that normally limit the resolution of analog-to-digital converters of this type, i.e., component matching, amplifier nonlinearity, finite gain, settling time, and signal dynamic range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.