Sigma-delta oversampled analog-to-digital converter network with chopper stabilization
US5148167A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 1991 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Jan 24, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/414
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an oversampling interpolative analog-to-digital converter having a sigma-delta modulator followed in cascade by a decimation filter, the decimation filter supplies digital output signals for the oversampling analog-to-digital converter at an output rate that is a submultiple 1/R of an oversampling rate at which digital samples of an input signal for said decimation filter are supplied. The chopping rate of the chopper-stabilized amplifier is a multiple of the output sample rate of the decimation filter to place the fundamental and the harmonics of the chopping at the frequencies corresponding to the zeroes in the decimation filter response, better to keep remnants of the chopper stabilization from appearing in the output samples from the decimation filter. The chopper stabilization moves the flicker (or 1/f) noise of the amplifier in the frequency spectrum from baseband to sidebands of the chopping frequency, and the chopper-stabilized amplifier is operated at a chopping rate higher than said output rate, to reduce the amplitude of the lower sideband as aliased into the baseband. The chopper-stabilized amplifier is operated at a chopping rate lower than half said oversampling ra…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.