Semiconductor memory device with built-in test circuit and method for testing the same
US5148398A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1990 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Jul 3, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a test mode function and a plurality of memory blocks each having memory cells arranged in a matrix and a method for testing the device. The device includes a unit for writing identical data in each memory cell of the plurality of memory blocks, a unit for simultaneously reading data of one bit from each of the plurality of memory blocks, a unit for detecting coincidence or non-coincidence of the read bits and outputting a result of the detection, and a unit for sequentially outputting the read bits one by one when the result is the non-coincidence. As a result, an address of a "failing" bit can be detected to facilitate a failure analysis, thereby reducing test time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.