Sense amplifier circuitry selectively separable from bit lines for dynamic random access memory
US5148399A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1991 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | May 31, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory device includes a sense amplifier circuit having a first transistor coupling section connected between a pair of bit lines and a pair of sense amplifier nodes. The first transistor coupling section selectively connects the bit lines and the sense amplifier nodes in response to a first control signal. The sense amplifier circuit further includes a first sense amplifier connected between the sense amplifier nodes so as to selectively discharge one of the sense amplifier nodes and a second sense amplifier connected between the sense amplifier nodes so as to selectively charge the other one of the sense amplifier nodes. The first control signal can have a first voltage substantially intermediate a potential equal to a potential threshold of a transistor in the first transistor coupling section and the sum of a potential equal to the potential threshold and a precharge potential at the beginning of a sense operation. At these voltage levels, the first transistor is operative to decouple a first sense node from a first bit line when a selected memory cell stores a logic ONE level while a second transistor connects a second sense node with as second bit line. …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.