Pipeline having an integral cache which processes cache misses and loads data in parallel
US5148536A · kind A · utility
106Cited by
26References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 1988 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Jul 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.