Digitally controlled monolithic switch matrix using selectable dual gate FET power dividers and combiners
US5150083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1990 |
| Grant date | Sep 22, 1992 |
| Priority date | — |
| Expiry date | Aug 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
There is described a 2.times.2 switch matrix which includes four 1.times.1 switch matrix modules. Each 1.times.1 switch matrix module consists of an active power divider switch (APDS), an active power combiner switch (APCS) and an air bridge crossover. Additional APDSs and APCSs are utilized in the matrix to compensate for path length differences between different input to output signal paths thus providing good phase and amplitude tracking. The basic switch matrix modules are utilized to form a 2.times.2 switch matrix whereby two primary input ports can be connected to any one of two primary output ports. The 2.times.2 switch matrix is utilized to formulate larger matrix arrays as N.times.M configuration. Each of the active power divider switches and power combiner switches utilize two separate dual gate FETs which are suitably interconnected, depending upon whether the circuit is to be used as a power combiner or power divider. The other gate electrodes of the dual gate FETs are used as control terminals to receive an adequate bias voltage to therefore determine the power distribution or power combination characteristics of each of the devices and hence to control the coupling be…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.