Register file capable of high speed read operation
US5150326A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1990 |
| Grant date | Sep 22, 1992 |
| Priority date | — |
| Expiry date | Oct 23, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a matrix array of registers, each register includes a latch having first and second terminals. First and second write transfer gates are responsive to a potential at a write address line for establishing a path from a first write data line to the first terminal of the latch and a path from a second write data line to the second terminal of the latch. A first junction is formed between series-connected N-channel MOS transistors whose gates are respectively coupled to the first and second terminals of the latch, and a second junction is likewise formed between series-connected N-channel MOS transistors whose gates are respectively coupled to the first and second terminals of the latch. First and second read transfer gates are respectively formed by N-channel MOS transistors which are responsive to a potential at a read address line for establishing a path from the first junction to a first read data line and a path from the second junction to a second read data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.