Clock multiplier/jitter attenuator
US5150386A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 1989 |
| Grant date | Sep 22, 1992 |
| Priority date | — |
| Expiry date | Feb 9, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/061
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock multiplier/jitter attenuator circuit provides a stable clock which is a multiple frequency of the average frequency of an external digital data stream. The external data is written into successive storage cells of a FIFO at its own clock rate and read out of the FIFO at the rate of an internal clock signal which is formed by frequency dividing the stable clock. The relative locations of the cell being written into and the cell being read out of are determined at periodic time intervals, and these relative locations are used to adjust the frequency of an internal oscillator which generates the stable clock. The instantaneous jitter on the digital data stream is absorbed by the FIFO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.