Integrated circuit device having improved substrate capacitance isolation
US5151775A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1991 |
| Grant date | Sep 29, 1992 |
| Priority date | — |
| Expiry date | Oct 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device having improved substrate capacitance isolation for use in a ultra low capacitance probe or an input to an oscilloscope or the like has an electrically conductive layer formed directly underneath an input node on the integrated circuit. The electrically conductive layer has a geometry substantially equal to the input node and is driven by a voltage output from a high impedance unity gain circuit. In one embodiment, the electrically conductive layer is formed in the first metal layer of the integrated circuit while an alternate embodiment an emitter region of a semiconductor device in the high impedance circuit is used as the electrically conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.