MOS array multiplier cell
US5151875A · kind A · utility
81Cited by
7References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1991 |
| Grant date | Sep 29, 1992 |
| Priority date | — |
| Expiry date | Oct 2, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5338
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a multiplier selector built of a matrix of identical selection elements, a single field effect transistor (FET) switch and an inverter. Each of the selection elements consists of an N-channel FET, a P-channel FET and an inverter. Each equivalence circuit utilizes six transistors: four FET's and an inverter. Total cell device count is 31 to 39 transistors, depending on implementation alternatives.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.