High resolution frequency synthesis
US5152005A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1991 |
| Grant date | Sep 29, 1992 |
| Priority date | — |
| Expiry date | Oct 15, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The synthesizer includes an output PLL having a divide-by-N1 divider in its feedback loop. The output PLL is couples through frequency offset circuitry to receive a reference signal from a driver PLL having a divide-by-N2 divider in its feedback loop. Another divide-by-N1 divider coupled a reference oscillator to the driver PLL. The reference oscillator provides another reference signal. As a result, the setting for N1 controls the course frequency tuning and the setting for N2 controls the fine frequency tuning of the synthesizer which provides any one of a plurality of selectable predetermined output frequencies. The adjacent selectable frequencies are closer together than the frequencies of the reference signals. The synthesizer has a simple configuration and provides a high degree of output frequency resolution, fast acquisition and low noise.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.