Programmable output drive circuit
US5153450A · kind A · utility
85Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 16, 1991 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Jul 16, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable output driver circuit is provided having multiple drive capabilities for optimizing noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.