Biasing network for use with field effect transistor ring mixer
US5153469A · kind A · utility
14Cited by
3References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 1991 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Apr 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A biasing network for use in conjunction with a mixer employing field effect transistors which provides for minimum conversion loss over a range of process and temperature conditions. The biasing circuit includes a first field effect transistor having a small gate periphery which is configured as a current source, a second or reference field effect transistor having a gate periphery substantially equal to the gate peripheries of the transistors in the mixer to which the biasing circuit is providing DC biasing voltages and a voltage divider which is functional in defining operating conditions for the reference transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.