System for testing internal nodes in receive and transmit FIFO's
US5153509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1991 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Feb 12, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus-oriented integrated circuit chip containing devices such as Receive and Transmit FIFO's further includes a testing circuit for testing normally inaccessible internal nodes in a FIFO device. The testing circuit includes test mode control register for storing the externally supplied test addresses of selected internal nodes of a FIFO device. A decoder, responding to a test command from a host microprocessor, selects the test addresses from the test mode control register and supplies them instead of other addresses to an internal address bus. A test decoder responds only to the test addresses on the internal address bus for enabling the transfer of data between the selected internal nodes and a data bus, thereby enabling bus access of the normally inaccessible internal nodes of a FIFO device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.