Field effect transistor
US5153683A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 1991 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Mar 22, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A field effect transistor having an asymmetric gate includes high dopant concentration source and drain regions. The drain region is shallower and of lower dopant concentration than the source region. The drain is spaced from the gate electrode. Therefore, an ideal FET having a reduced short channel effect and having a lower source resistance and high current drivability (gm) is obtained. When the drain region is produced by ion implantation through a film and the source region is produced by the implantation directly into the substrate, only the drain region is separated from the gate. When the insulating film on the source region is separated from the insulating film on the drain region, the insulating film on the source region is reliably selectively removed, whereby high controllability is obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.