Nonvolatile semiconductor memory device with offset transistor
US5153684A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 1991 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Jul 24, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Source and drain regions of a second conductivity type are formed in a stripe form in the surface area of a semiconductor substrate of a first conductivity type. A first insulation film is formed on the source and drain regions of the substrate. A second thin insulation film having a tunnel effect is formed on that part of the substrate which lies between the source and drain regions. A floating gate is formed on the second insulation film. A third insulation film is formed on the first insulation film, the floating gate and that part of the substrate which lies between the source and drain regions and on which the second insulation film is not formed. A control gate is formed on the third insulation film in a stripe form extending in a direction which intersects the source and drain regions. An impurity region of the first conductivity type having an impurity concentration higher than the substrate is formed in the substrate except the source and drain regions and the portions lying below the control gate. A floating gate transistor is constituted to include the substrate, source and drain regions, second insulation film, floating gate, third insulation film and control gate. An o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.