Semiconductor memory device having bit lines formed of an interconnecting layer of lower reflectance material than the material of the word lines
US5153689A · kind A · utility
6Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 1989 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Sep 8, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell of a semiconductor memory device comprises one MOS transistor (3) and one stacked capacitor (4). One of the source/drain regions (8a, 8b) of the MOS transistor is connected to a bit line (2a, 2b). The bit line is formed from a contact portion to the source/drain regions of the MOS transistor to a portion above the stacked capacitor. The bit line is formed of a metal having high melting point, a silicide of a metal having high melting point or a polycide. Since this material has low reflectance against exposing light, the precision in patterning the interconnection is improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.