Layout of large multistage interconnection networks technical field
US5153843A · kind A · utility
26Cited by
5References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 1, 1988 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Apr 1, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for laying out large multistage interconnection networks. The invention provides for the division of a network into sub-networks which may be maintained on printed circuit boards and then provides for the addition of switching circuitry at the inputs or outputs of such boards such that pin locations on the boards may be swapped with each other to allow for a parallel interconnection of corresponding pins between the boards. Such parallel interconnection eliminates the existence of rat's nests in the wiring harness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.