Method and apparatus for modifying two's complement multiplier to perform unsigned magnitude multiplication
US5153850A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1990 |
| Grant date | Oct 6, 1992 |
| Priority date | — |
| Expiry date | Aug 24, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/523
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two's complement multiplier is combined with additional circuit elements and implemented in an integrated circuit to provide a multiplier of selectively operating in two's complement or unsigned magnitude format. To achieve an unsigned magnitude product, the additional circuitry modifies or leaves unchanged the high-order half of the two's complement product as needed. Modification occurs when the most-significant bit of either or both multiplicand signals is a "1". When a multiplicand signal has a most-significant bit of "1", the non-most significant bits of the other multiplicand signal are added to the two's complement product to derive the unsigned magnitude product. Such an implementation results in insignificant speed loss and comparatively minor increase in the required silicon area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.