Method for fabricating metal core layers for a multi-layer circuit board
US5153986A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1991 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Jul 17, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of fabricating a multilayer electronic circuit package. The multilayer circuit package has at least one layer that is a circuitized, polymer encapsulated metal core. According to the method of the invention a metal foil is provided for the metal core of the layer. This metal core foil may be provided as a single unit or in a continuous, roll to roll, process. The vias and through holes are drilled, etched, or punched through the metal foil. An adhesion promoter is then applied to the perforate metal foil for subsequent adhesion of polymer to the foil. The dielectric polymer is then applied to the perforate metal foil core by vapor depositing, chemical vapor depositing, spraying or electrophoretically depositing, a thermally processable dielectric polymer or precursor thereof onto exposed surfaces of the perforate metal foil including the walls of the through holes and vias. The dielectric polymer or precursor thereof is then thermally processed to form a conformal dielectric, polymeric coating on surfaces of the perforate metal foil, including the interior surfaces of the vias and through holes. This dielectric, polymeric coating may then be circuitized, and c…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.