Method of forming T-gate structure on microelectronic device substrate
US5155053A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1991 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | May 28, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/951
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A T-gate structure (28a) is fabricated on a microelectronic device substrate (10) using a trilevel resist system in combination with a two-step reactive ion etching (RIE) technique utilizing an oxygen plasma. The trilevel resist consists of a planarizing resist layer (12), masking layer (14) and imaging resist layer (16), which are formed on the surface (10a) of the substrate (10). A focused ion beam (18) is then used to expose the uppermost imaging layer (16) with an image having a width equal to the desired gate length of the T-gate structure (28a). The imaged area is developed and etched to form an opening (14a,16a) of the same width through the imaging layer (16) and also through the masking layer (14). In the first oxygen RIE step, the planarizing resist layer (12) is etched isotropically through the opening (14a,16a), partially down to the substrate surface (10a) to form a cavity (12a) having a width which is larger than the width of the opening (14a,16a). The second oxygen RIE step is used to etch the planarizing resist layer (12) through the opening (14a,16a) completely down to the substrate surface (10a) to form a notch (12a) underneath the cavity (12a) having a width subs…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.