Clock switching circuit and method for preventing glitch during switching
US5155380A · kind A · utility
67Cited by
1References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1991 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Apr 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1252
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock switching circuit comprises a multiplexer, a gate, a first detector, a second detector and a state machine. The multiplexer receives two clock signals and outputs one of them through the gate. The first detector is coupled to the output of the multiplexer and the second detector is coupled to the output of the gate. The state machine controls the output of the gate and the multiplexer in response to signals from the first and second detector, and prevent glitches from being output by the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.