Low di/dt BiCMOS output buffer with improved speed
US5155392A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 1991 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Jun 17, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low di/dt BiCMOS output buffer with improved speed for a device such as a memory includes an input portion, a level shifter, first and second logic portions, and an output stage. The input portion provides first and second signals respectively in response to positive and negative differences between true and complementary input signals. The level shifter decreases the first and second signals by a predetermined amount to provide third and fourth signals. When selected, the first and second logic portions provide a pullup signal and a pulldown signal respectively in response to the third and fourth signals to the output stage. The output stage provdes a data output signal at a logic high voltage in response to the pullup signal and at a logic low voltage in response to the pulldown signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.