Circuit and method for dynamically generating a clock signal
US5155451A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 1992 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Feb 18, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator (30) dynamically generates a system clock in response to a high or a low frequency oscillator. An amplified oscillator input is provided to a first input of a multiplexor (62), a divider (56), and a comparator circuit (58, 60). Divider (56) divides an oscillator input frequency to provide a divided input to a second input of multiplexor (62). Comparator circuit (58,60) compares the input frequency with a reference frequency to determine whether the input frequency is high or low. If the input frequency is low, multiplexor (62) is enabled to provide the oscillator input as the system clock. If the input frequency is high, multiplexor (62) provides the divided input as the system clock. Additionally, comparator circuit (58,60) provides a control signal to enable an amplifier (50) to amplify the oscillator input using a high or low gain factor in accordance with the input frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.