Asynchronous serial data receiver with capability for sampling the mid-point of data bits
US5155486A · kind A · utility
10Cited by
9References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 28, 1990 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Mar 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/068
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An asynchronous serial data receiver utilizes plural samples of each data bit in a word to assure detection and reading of the midpoint of each bit to mitigate problems associated with noise and mismatches between the data and sampling rates. To this end, a shift register having plural stages for each bit samples the data stream at a clock rate which is a multiple of the data rate which provides multiple samples of each incoming bit. When the data word is fully read into the shift register the start bit is detected and initiates a parallel transfer of the data word using bit values taken from the midpoint of each bit period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.