Complementary field effect transistors having strained superlattice structure

US5155571A · kind A · utility

Assignee

• The Regents of the University of California · US

Inventors

• Kang L. Wang · Santa Monica, US
• Jason Woo · Vaughan, CA

Key dates

• Filing date: Aug 6, 1990
• Grant date: Oct 13, 1992
• Expiry date: Aug 6, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

The carrier mobilities for both electrons and holes in complementary field effect transistor structures such as CMOS and CMOD devices are increased by using strained Ge.sub.x Si.sub.1-x /Si layers for the carrier conduction channels. The carrier mobilities for the holes and electrons can be of substantially the same magnitude which is advantageous for complementary logic applications. The complementary FET structures can be advantageously employed with bipolar devices in integrated circuits.