Semiconductor integrated circuit device and method of testing the same
US5155701A · kind A · utility
36Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 8, 1990 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Jun 8, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EPROM and a method of testing the former, in which a defective memory cell caused by defects in the insulating films between a substrate and a floating gate and between the floating gate and a control gate can be tested without writing any data in the individual memory cells by holding data lines to a low potential and word lines fed with a voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.