BiCMOS bit line load for a memory with improved reliability
US5155703A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 6, 1990 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | Jul 6, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) bit line load for a memory with improved speed write recovery and improved reliability. Comprises a first bipolar transistor, a resistor, and a second and third bipolar transistors respectively coupled to first and second bit lines of a differential bit line pair. The improvement in speed is accomplished through the use of the bipolar transistors which generally switch faster than corresponding MOS transistors. The first bipolar transistor has a collector coupled to a power supply voltage terminal, a base for receiving a bias signal, and an emitter coupled to the collectors of the second and third bipolar transistors. The resistor is coupled between the collector and emitter of the first bipolar transistor. The bit line load has improved reliability by preventing self-boosting at the bases of the second and third bipolar transistors by decreasing their collector voltages enough during switching to bias them into saturation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.