Fault recovery in systems utilizing redundant processor arrangements
US5155729A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1990 |
| Grant date | Oct 13, 1992 |
| Priority date | — |
| Expiry date | May 2, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus to prevent endless switchover attempts between processors in redundant processor systems where each processor resets an associated watch dog timer (WDT). Whenever a WDT times out, WDT sends a restart signal to its associated processor and a failure signal to switchover control logic. The switchover control logic causes a switch from the active processor to the standby processor if the standby processor is healthy and is properly resetting its WDT and, if the standby processor is not, the switchover control logic will generate a signal to cause a cold reboot of the entire system. However, if the standby processor is healthy, the switchover control logic will generate a signal to cause a switchover to the standby and will generate a signal to increment a switchover counter. The value of the switchover counter is compared with a predetermined threshold value. If the value of the switchover counter matches the predetermined threshold value, a signal is generated to cause a cold reboot of the entire system. A timer associated with the switchover counter periodically clears the switchover counter. Thus, if the system is switching back and forth between the redundant processors …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.