Conditional clocking of the second latch of a shift register ratch
US5157286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1990 |
| Grant date | Oct 20, 1992 |
| Priority date | — |
| Expiry date | Feb 23, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/00
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A logic circuit is presented comprising a plurality of registers 30, 39; each register 30 having first register latches 31, 41 for clocking data into the register 30 in response to a first clock signal 37 and second register latches for clocking data out of the register in response to a second clock signal 38, and combinatorial logic comprising address logic 4 for addressing data to a register and first suppression logic 33 for inhibiting the first clock signal input to the register in response to the address logic, wherein the logic circuit further comprises second suppression logic 34, 35 for inhibiting the second clock signal input to the register in collective response to the address logic and the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.